Nitride semiconductor substrate, semiconductor device, and methods for manufacturing nitride semiconductor substrate and semiconductor device

ABSTRACT

A nitride semiconductor substrate having a main surface serving as a semipolar plane and provided with a chamfered portion capable of effectively preventing cracking and chipping, a semiconductor device fabricated using the nitride semiconductor substrate, and a method for manufacturing the nitride semiconductor substrate and the semiconductor device are provided. The nitride semiconductor substrate includes a main surface inclined at an angle of 71° or more and 79° or less with respect to the (0001) plane toward the [1-100] direction or inclined at an angle of 71° or more and 79° or less with respect to the (000-1) plane toward the [−1100] direction; and a chamfered portion located at an edge of an outer periphery of the main surface. The chamfered portion is inclined at an angle θ 1  or θ 2  of 5° or more and 45° or less with respect to adjacent one of the main surface and a backside surface on a side opposite to the main surface. Accordingly, cracking and chipping occurring from the edge of the outer periphery of the nitride semiconductor substrate can be effectively suppressed.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a nitride semiconductor substrate, asemiconductor device and methods for manufacturing the nitridesemiconductor substrate and the semiconductor device, and moreparticularly to a nitride semiconductor substrate having a main surfaceserving as a semipolar plane, a semiconductor device, and methods formanufacturing the nitride semiconductor substrate and the semiconductordevice.

2. Description of the Background Art

A nitride semiconductor substrate such as a GaN substrate having anenergy band gap of 3.4 eV and a high thermal conductivity has beenattracting attention as material for a semiconductor device such as apower electronic device and an optical device of a short wavelength. Inorder to prevent chipping, cracking and the like of the substrate, it isproposed to provide a chamfered portion at the edge of the outerperiphery in the GaN substrate which is an example of theabove-described nitride semiconductor substrate (for example, seeJapanese Patent Laying-Open No. 2004-319951).

However, Japanese Patent Laying-Open No. 2004-319951 as described abovediscloses a substrate having a main surface corresponding to thec-plane, but fails to disclose a nitride semiconductor substrate havinga main surface serving as a semipolar plane (main surface inclined fromthe c-plane). Furthermore, it is not known what type of chamferedportion is formed at the edge of the outer periphery in the nitridesemiconductor substrate conventionally having such a semipolar plane asa main surface in order to effectively reduce cracking and chipping ofthe nitride semiconductor substrate.

SUMMARY OF THE INVENTION

The present invention has been made in order to solve theabove-described problems, and an object of the present invention is toprovide a nitride semiconductor substrate having a main surface servingas a semipolar plane and provided with a chamfered portion capable ofeffectively preventing cracking and chipping; and a semiconductor devicefabricated using the nitride semiconductor substrate, and methods formanufacturing the nitride semiconductor substrate and the semiconductordevice.

The inventors of the present invention have made an earnest study todiscover that the nitride semiconductor substrate capable of improvingthe oscillation yield when fabricating a semiconductor laser device hasa main surface inclined at an angle of 71° or more and 79° or less withrespect to the (0001) plane toward the [1-100] direction, or a mainsurface inclined at an angle of 71° or more and 79° or less with respectto the (000-1) plane toward the [−1100] direction. The inventors alsodiscovered the shape of the chamfered portion capable of effectivelysuppressing cracking and chipping occurring in the nitride semiconductorsubstrate during the process of manufacturing the semiconductor deviceand during handling of the nitride semiconductor substrate by employingthe nitride semiconductor substrate having the above-described mainsurface for the semiconductor device.

The nitride semiconductor substrate according to the present inventionincludes a main surface inclined at an angle of 71° or more and 79° orless with respect to a (0001) plane toward a [1-100] direction orinclined at an angle of 71° or more and 79° or less with respect to a(000-1) plane toward a [−1100] direction; and a chamfered portionlocated at an edge of an outer periphery of the main surface. Thechamfered portion is inclined at an angle of 5° or more and 45° or lesswith respect to adjacent one of the main surface and a backside surfaceon a side opposite to the main surface.

The nitride semiconductor substrate according to the present inventionhas a main surface which allows the yield to be improved when asemiconductor device is fabricated. Furthermore, cracking and chippingoccurring from the edge of the outer periphery in the nitridesemiconductor substrate can also be suppressed. Consequently, defectsoccurring in the nitride semiconductor substrate resulting from theabove-mentioned cracking and chipping can be suppressed, to allow anincrease in the yield of the nitride semiconductor substrate.

A method for manufacturing a nitride semiconductor substrate accordingto the present invention includes the steps of: preparing a nitridesemiconductor substrate having a main surface inclined at an angle of71° or more and 79° or less with respect to a (0001) plane toward a[1-100] direction or inclined at an angle of 71° or more and 79° or lesswith respect to a (000-1) plane toward a [−1100] direction; andchamfering an edge of an outer periphery of the main surface of thenitride semiconductor substrate. The step of chamfering the edgeincludes the step of forming a chamfered portion inclined at an angle of5° or more and 45° or less with respect to adjacent one of the mainsurface and a backside surface on a side opposite to the main surface.

In this way, the nitride semiconductor substrate according to thepresent invention can be manufactured.

The semiconductor device according to the present invention is asemiconductor device fabricated using the above-described nitridesemiconductor substrate. In this case, since cracking and chipping ofthe nitride semiconductor substrate can be effectively suppressed, asemiconductor device providing a high manufacturing yield can beimplemented.

The method for manufacturing a semiconductor device according to thepresent invention includes the steps of preparing a nitridesemiconductor substrate using the above-described method formanufacturing the nitride semiconductor substrate; and forming anepitaxial layer on the main surface of the nitride semiconductorsubstrate. In this case, since cracking and chipping of the nitridesemiconductor substrate can be effectively suppressed, a semiconductordevice providing a high manufacturing yield can be implemented.

According to the present invention, cracking and chipping of the nitridesemiconductor substrate can be effectively suppressed, with the resultthat a semiconductor device providing a high yield can be manufactured.

The foregoing and other objects, features, aspects and advantages of thepresent invention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic plan view of the first embodiment of a nitridesemiconductor substrate according to the present invention.

FIG. 2 is a schematic cross-sectional view taken along a line II-II inFIG. 1.

FIG. 3 is a schematic diagram illustrating the plane orientation of eachof the main surface and the orientation flat of the nitridesemiconductor substrate shown in FIGS. 1 and 2.

FIG. 4 is a flowchart illustrating a method for manufacturing thenitride semiconductor substrate shown in FIGS. 1 and 2.

FIGS. 5 and 6 are schematic diagrams each illustrating a chamferingprocessing step (S20) shown in FIG. 4.

FIG. 7 is a partial cross-sectional schematic diagram showing amodification of the nitride semiconductor substrate shown in FIGS. 1 and2.

FIGS. 8 to 11 are partial cross-sectional schematic diagrams eachshowing a modification of the nitride semiconductor substrate shown inFIGS. 1 and 2.

FIG. 12 is a schematic plan view showing another modification of thenitride semiconductor substrate shown in FIGS. 1 and 2.

FIG. 13 is a schematic diagram illustrating the crystal orientation ofthe main surface and the second orientation flat of the nitridesemiconductor substrate shown in FIG. 12.

FIG. 14 is a schematic plan view illustrating another modification ofthe nitride semiconductor substrate shown in FIGS. 1 and 2.

FIG. 15 is an enlarged schematic diagram of a region R shown in FIG. 14.

FIGS. 16 and 17 are schematic plan views each illustrating anothermodification of the nitride semiconductor substrate shown in FIGS. 1 and2.

FIG. 18 is a schematic cross-sectional view of a light emitting elementserving as a semiconductor device fabricated using the nitridesemiconductor substrate according to the present invention.

FIG. 19 is a schematic cross-sectional view illustrating a lightemitting layer of the light emitting element shown in FIG. 18.

FIG. 20 is a cross-sectional schematic diagram showing the configurationhaving an electrode formed in the light emitting element shown in FIGS.18 and 19.

FIG. 21 is a schematic diagram showing a light emitting devicefabricated using the light emitting element shown in FIG. 20.

FIG. 22 is a cross-sectional view schematically showing a semiconductorlaser device fabricated in Example 1.

FIG. 23 is a schematic diagram showing the position of a waveguide inthe semiconductor laser device shown in FIG. 21 as seen from above.

FIG. 24 is a diagram schematically showing the crystal orientation ineach of the end face of the semiconductor laser device shown in FIG. 21and the main surface of the nitride semiconductor substrate.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The embodiments of the present invention will be hereinafter describedwith reference to the accompanying drawings, in which the same orcorresponding components are designated by the same referencecharacters, and description thereof will not be repeated. In addition,in this specification, each orientation is represented in squarebrackets “[ ]” and each plane is represented in round brackets “( )”.Although a negative index should be crystallographically represented tohave a negative sign (a bar (“−”)) attached on the figure, the negativesign (“−”) is placed in front of the figure in this specification. Itgoes without saying that the specific orientation and direction in thedescription also include the orientation and direction having therelationship equivalent thereto.

First Embodiment

Referring to FIGS. 1-3, the first embodiment of the nitridesemiconductor substrate according to the present invention will behereinafter described.

As shown in FIGS. 1 and 2, a nitride semiconductor substrate 10 aaccording to the present invention has an approximately circular shapeas seen in plan view and has an orientation flat 12 formed by linearlyprocessing a part of the edge of the outer periphery. Furthermore, onthe edge of the outer periphery of nitride semiconductor substrate 10 a,a topside chamfer 22 is formed which corresponds to a chamfered portionlocated on the main surface 11 side. Furthermore, on the outer peripheryof a backside surface 21 on the side opposite to main surface 11, abackside chamfer 23 is formed which corresponds to a chamfered portionlocated on the backside surface 21 side. At the edge of the outerperiphery of nitride semiconductor substrate 10 a, an edge face 24having a curved surface is formed so as to connect topside chamfer 22and backside chamfer 23. These topside chamfer 22, backside chamfer 23and edge face 24 constitute a chamfered portion (chamfer). Topsidechamfer 22 has a width L2 greater than a width L1 of backside chamfer23.

Topside chamfer 22 extends in the direction intersecting at an angle θ2with the direction in which main surface 11 extends. Furthermore,backside chamfer 23 extends in the direction intersecting at an angle θ1with the direction in which backside surface 21 extends. Angles θ1 andθ2 may be the same value or a different value. A damaged layer 25 isformed on the surface layer of each of topside chamfer 22, backsidechamfer 23 and edge face 24. As seen from FIG. 2, damaged layer 25formed in topside chamfer 22 has a thickness greater than that ofdamaged layer 25 formed in backside chamfer 23.

Main surface 11 corresponds to a plane inclined at an angle of 71° ormore and 79° or less with respect to the (0001) plane (c+ plane) towardthe [1-100] direction (m+ axis direction) or a plane inclined at anangle of 71° or more and 79° or less with respect to the (000-1) plane(c− plane) toward the [−1100] direction (m− axis direction), andpreferably corresponds to the (20-21) plane or the (−202-1) plane. It isto be noted that the plane orientation of main surface 11 may beinclined at a predetermined angle from the above-described planeorientation (20-21) or (−202-1).

The plane orientation of main surface 11 will be hereinafter describedwith reference to FIG. 3. As shown in FIG. 3, main surface 11 isinclined at an angle θ with respect to the (0001) plane toward the[1-100] direction (m+ axis direction). In other words, main surface 11is inclined at angle θ with respect to the [0001] direction (c-axisdirection) toward the [1-100] direction (m− axis direction). Angle θ is71° or more and 79° or less, preferably 73° or more and 77° or less, andmore preferably 74° or more and 76° or less. It is to be noted that the(20-21) plane or the (−202-1) plane is inclined at an angle ofapproximately 75° (=angle θ) with respect to the (0001) plane or the(000-1) plane toward the m+ axis direction or the m− axis direction. Them− axis direction herein corresponds to the [−1100] direction.

Furthermore, when the above-described angle θ is 71° or more and 79° orless, the yield of the semiconductor device (for example, asemiconductor laser device) fabricated using this nitride semiconductorsubstrate 10 a can be improved (for example, 50% or more). When angle θis 73° or more and 77° or less, the yield of the semiconductor device(for example, a semiconductor laser device) fabricated using nitridesemiconductor substrate 10 a can be further improved (for example, 75%or more). When angle θ is 74° or more and 76° or less, the yield of thesemiconductor device (for example, a semiconductor laser device)fabricated using nitride semiconductor substrate 10 a can be stillfurther improved (for example, 80% or more).

Furthermore, in nitride semiconductor substrate 10 a as described above,the chamfered portion is inclined at an angle of 5° or more and 45° orless with respect to one, which is adjacent to the chamfered portion, ofmain surface 11 and backside surface 21 on the side opposite to mainsurface 11 (angle θ1 or angle θ2 in FIG. 2). In this way, cracking andchipping occurring from the edge of the outer periphery of nitridesemiconductor substrate 10 a can be suppressed. Consequently, defectsoccurring in nitride semiconductor substrate 10 a resulting from theabove-mentioned cracking and chipping can be suppressed, to therebyallow the processing yield of nitride semiconductor substrate 10 a to beimproved. Furthermore, the yield of the semiconductor device (forexample, a semiconductor laser device) fabricated using nitridesemiconductor substrate 10 a can be improved.

Also, as shown in FIGS. 1 and 2, since the size of each of topsidechamfer 22 and backside chamfer 23 in the chamfered portion (forexample, width L1 and width L2 each corresponding to the chamferingamount) is different between main surface 11 and backside surface 21,main surface 11 and backside surface 21 can be distinguished from eachother by visually examining the size of each chamfer.

Furthermore, in the chamfered portion, the thickness of damaged layer 25on the main surface 11 side corresponding to the topside surface isdifferent from the thickness of damaged layer 25 on the backside surface21 side. Accordingly, the stability of the shape of nitridesemiconductor substrate 10 a can be improved.

Furthermore, referring to FIG. 1, orientation flat 12 is obtained bycutting out a part of the outer periphery of nitride semiconductorsubstrate 10 a in an arcuate shape in order to show the crystalorientation of nitride semiconductor substrate 10 a. In other words,orientation flat 12 corresponds to a linear area formed in a part of thecircle of main surface 11 as seen from above. It is to be noted that theinventors first found that, when the main surface corresponds to the(20-21) plane inclined at an angle of 75° with respect to the (0001)plane toward the [1-100] direction or the (−202-1) plane inclined at anangle of 75° with respect to the (000-1) plane toward the [−1100]direction, cleavage readily occurs at and near the (−1017) plane or the(10-1-7) plane approximately orthogonal to the main surface. Thus,orientation flat 12 corresponds to the (−1017) plane, the (10-1-7) planeor the plane inclined at angle of −0.5° or more and 0.5° or less fromthese planes, more preferably corresponds to the (−1017) plane, the(10-1-7) plane or the plane inclined at an angle of −0.2° or more and0.2° or less from these planes, and most preferably corresponds to the(−1017) plane or the (10-1-7) plane.

The plane orientation of orientation flat 12 will be hereinafterdescribed with reference to FIG. 3. As shown in FIG. 3, orientation flat12 is at and near the (−1017) plane or the (10-1-7) plane. The (−1017)plane and the (10-1-7) plane are approximately orthogonal to the (20-21)plane or the (−202-1) plane (intersected at an angle of 90.10°).Accordingly, orientation flat 12 is approximately orthogonal to mainsurface 11. These (−1017) plane and (10-1-7) plane each are differentfrom the conventional cleavage plane such as the conventional c-plane,m-plane or a-plane.

The direction of the normal to the (−1017) plane or the (10-1-7) planeextends approximately in the [−1014] direction or the [10-1-4]direction.

Therefore, it has been found for the first time that orientation flat 12can be readily formed in the plane orthogonal to the [−1014] directioncorresponding to the direction of the normal to the (−1017) plane whenthe main surface is inclined at an angle of 71° or more and 79° or lesswith respect to the (0001) plane toward the [1-100] direction, or in theplane orthogonal to the [10-1-4] direction corresponding to thedirection of the normal to the (10-1-7) plane when the main surface isinclined at an angle of 71° or more and 79° or less with respect to the(000-1) plane toward the [−1100] direction.

Furthermore, the present inventors have made an earnest study to findout that, from a different point of view, the (−1017) plane, the(10-1-7) plane, or the plane inclined at an angle of −0.5° or more and0.5° or less from these planes has a tendency to easily cleave.Accordingly, orientation flat 12 can be readily formed in the plane asdescribed above. Furthermore, orientation flat 12 can be readily formedin the (−1017) plane, the (10-1-7) plane, or the plane inclined at anangle of −0.2° or more and 0.2° or less from these planes. In addition,orientation flat 12 may be formed in the (−1017) plane or the (10-1-7)plane.

It is to be noted that the c+ plane represents the (0001) plane having aGa polarity, and the c−plane represents the (000-1) plane having an Npolarity. The m− axis direction includes the [1-100] direction, the[10-10] direction, the [−1100] direction, the [−1010] direction, the[01-10] direction, the [0-110] direction, and the direction parallel tothese directions.

Furthermore, the (−1017) plane lies on the side opposite to the (10-1-7)plane.

Nitride semiconductor substrate 10 a is, for example,Al_(x)In_(y)Ga_((1-x-y))N (0≦x≦1, 0≦y≦1, x+y≦1), preferablyAl_(x)Ga_((1-x))N (0≦x≦1), and more preferably GaN. Furthermore, whenthe nitride semiconductor substrate is in the shape of a circle, thediameter is preferably 10 mm or more, more preferably 30 mm or more,further preferably 2 inches or more, and still further preferably 3inches or more. Also, when the nitride semiconductor substrate has aquadrangular shape, the side length is preferably 10 mm or more, morepreferably 18 mm or more, and further preferably 30 mm or more. It ispreferable that the substrate has a thickness of 100 μm or more and 1000μm or less. The substrate can be handled when the thickness is 100 μm ormore, and can be cut when the thickness is 1000 μm or less. It is morepreferable that the thickness is 300 μm or more and 400 μm or less.

Referring to FIG. 4, the method for manufacturing the nitridesemiconductor substrate shown in FIGS. 1 and 2 will be described.

Referring to FIG. 4, the substrate preparing step (S10) is first carriedout. Specifically, in the step (S10), a nitride semiconductor substratefabricated, for example, by the vapor deposition method is prepared.Although the nitride semiconductor substrate can have an arbitraryplanar shape, it may have a circular shape, for example. Furthermore,the nitride semiconductor substrate having a circular shape may have adiameter of 2 inches (approximately 50 mm), for example. The nitridesemiconductor substrate can be configured to contain dopants to berendered an arbitrary conductivity type (for example, an n-type). Forexample, silicon (Si) and oxygen (O) can be applied as dopants that areused for the substrate to be rendered n-type conductivity.

In this step (S10), it is possible to carry out the process step forsetting the outer diameter of the ingot of the nitride semiconductorgrown, for example, by the vapor deposition method to a predeterminedvalue (for example, outer-periphery grinding step and core-drillingstep), and the step of obtaining a wafer by slicing the processed ingot.

It is to be noted that the nitride semiconductor substrate prepared inthis step (S10) may be manufactured by an arbitrary method. For example,the nitride semiconductor substrate manufactured by the following methodmay be prepared.

An underlying substrate is prepared. The underlying substrate to beprepared may be made of the material identical to or different from thatof nitride semiconductor substrate 10 a to be grown. As theabove-described underlying substrate, for example, a GaN substrate, agallium arsenide (GaAs) substrate, a sapphire (Al₂O₃) substrate, a zincoxide (ZnO) substrate, a silicon carbide (SiC) substrate, and the likecan be used.

Then, a nitride semiconductor crystal is formed on the underlyingsubstrate. The method for growing a nitride semiconductor crystal is notparticularly limited, but may include the vapor deposition method suchas the sublimation method, the HYPE (hydride vapor phase epitaxy)method, the MOCVD (metal organic chemical vapor deposition) method, andthe MBE (molecular beam epitaxy) method; and the liquid phase growthmethod such as the flux method and the ammonothermal method.

Then, a nitride semiconductor substrate is cut out from the nitridesemiconductor crystal processed to achieve an outer diameter having apredetermined value. In this case, the nitride semiconductor substrateis cut out such that the main surface is inclined at an angle of 71° ormore and 79° or less with respect to the (0001) plane toward the [1-100]direction. For example, when the main surface of the underlyingsubstrate corresponds to the c+ plane, the nitride semiconductor crystalgrows in the c+ axis direction. For this reason, the nitridesemiconductor substrate is cut out along the flat plane parallel to mainsurface 11 in FIG. 3 (the plane inclined at angle θ with respect to thec+ plane toward the m+ axis direction). When the nitride semiconductorsubstrate is cut out such that the main surface is inclined at an angleof 71° or more and 79° or less with respect to the (000-1) plane towardthe [−1100] direction, the (0001) plane is on the side opposite to the(000-1) plane, and accordingly, the bottom of the above-mentionedcrystal corresponds to the (000-1) plane. Therefore, it is onlynecessary to cut out the nitride semiconductor substrate such that themain surface is inclined at an angle of 71° or more and 79° or less withrespect to that plane toward the [−1100] direction.

The method for cutting out the nitride semiconductor substrate is notparticularly limited, and, for example, a mechanical removal method suchas cutting may be employed. Cutting means that a slicer provided with anouter peripheral blade, a slicer provided with an inner peripheralblade, a wire saw or the like is used to mechanically cut out nitridesemiconductor substrate 10 a from the nitride semiconductor crystal.

It is to be noted that the underlying substrate may be removed, ifnecessary. Although the method for removing the underlying substrate isnot particularly limited, for example, a method such as cutting,grinding and the like can be employed. Cutting means that a slicerprovided with an outer peripheral blade made of an electrodepositeddiamond wheel, a wire saw or the like is used to mechanically cut(slice) the interface between the nitride semiconductor crystal and theunderlying substrate; to apply or spray a laser pulse or water moleculeson the interface between the nitride semiconductor crystal and theunderlying substrate; to cause cleavage along the crystal lattice plane;and to mechanically cut apart the nitride semiconductor crystal and theunderlying substrate by the chemical method such as etching.Furthermore, grinding means that a grindstone is rotated to be broughtinto contact with the surface of the underlying substrate for scrapingin the thickness direction. In order to remove the underlying substrateby grinding, the underlying substrate is mechanically scraped off, forexample, by the grinding apparatus provided with a diamond grindstone,and the like.

The process of fabricating a nitride semiconductor substrate having amain surface inclined at an angle of 71° or more and 79° or less withrespect to the (0001) plane toward the [1-100] direction or inclined atan angle of 71° or more and 79° or less with respect to the (000-1)plane toward the [−1100] direction is not limited to the process ofcutting out the nitride semiconductor substrate at a desired angle fromthe nitride semiconductor crystal grown in the c-axis direction.Furthermore, a nitride semiconductor substrate can also be manufacturedby further growing a nitride semiconductor crystal on the main surfaceof the nitride semiconductor substrate obtained as described above,cutting out the grown nitride semiconductor crystal along the planeparallel to the main surface of the crystal substrate to produce anitride semiconductor substrate, and processing the main surface of thenitride semiconductor substrate in the same manner as described above.The number of nitride semiconductor substrates used as an underlyingsubstrate for further growing (repeatedly growing) the above-mentionednitride semiconductor crystal is not necessarily limited to one, but aplurality of crystal substrates of small size may be used. Thesubstrates can be joined together during the repeated growth tofabricate a single crystal. Furthermore, the crystal substrate cut outfrom the nitride semiconductor crystal joined during the repeated growthmay also be used as an underlying substrate for another repeated growth.Thus, the production costs can be reduced by repeatedly using andgrowing the nitride semiconductor crystal.

Then, as shown in FIG. 4, the chamfering processing step (S20) iscarried out. In this step (S20), a chamfer (chamfered portion) as shownin FIG. 2 is formed at the edge of the outer periphery of nitridesemiconductor substrate 10 a. Specifically, for example, a rubbergrindstone 30 as shown in FIGS. 5 and 6 is used to process the edge ofthe outer periphery of nitride semiconductor substrate 10 a.

For example, as shown in FIG. 5, rubber grindstone 30 having a surface31 in the conical shape is used to grind the angular portion of the edgeof the outer periphery of nitride semiconductor substrate 10 a. In thiscase, the area where surface 31 of rubber grindstone 30 is in contactwith the edge of nitride semiconductor substrate 10 a is linearlyformed. As a result, topside chamfer 22 shown in FIG. 2 is formed. Also,rubber grindstone 30 shown in FIG. 5 is rotated, as shown by an arrow inFIG. 5, about the axis connected to rubber grindstone 30. Furthermore,angle θ2 formed between the direction in which main surface 11 shown inFIG. 2 extends and the direction in which topside chamfer 22 extends canbe arbitrarily changed by adjusting the angle formed between surface 31of rubber grindstone 30 and main surface 11 of nitride semiconductorsubstrate 10 a.

Furthermore, backside chamfer 23 shown in FIG. 2 can be formed bybringing rubber grindstone 30 shown in FIG. 5 into contact with the edgeof nitride semiconductor substrate 10 a from the backside surface 21side and grinding the edge.

Furthermore, edge face 24 having a curved surface shown in FIG. 2 isobtained by bringing rubber grindstone 30 having a surface 32 formed ina curved shape into contact with the edge face of nitride semiconductorsubstrate 10 a and grinding the edge face. Although the conditions suchas the grain size of rubber grindstone 30 as described above can beselected as appropriate, rubber grindstone 30 having a grain size, forexample, of #300 to #3000 may be used.

In this chamfering processing step (S20), a microscope is used to detectthe difference of the surface conditions between main surface 11 andbackside surface 21 of nitride semiconductor substrate 10 a fordistinguishing between the topside surface and the backside surface.Then, in this step (S20), the processing amount in each of topsidechamfer 22 and backside chamfer 23 is changed (for example, eachchamfering amount and angles θ1 and θ2 are changed) to allow the topsidesurface and the backside surface of the substrate to be readilydistinguished from each other in the subsequent steps.

Then, the backside surface grinding step (S30) is carried out. In thisstep (S30), backside surface 21 of nitride semiconductor substrate 10 ais ground. In the grinding process, the conventionally well-knownarbitrary methods can be employed. This step (S30) aims to form nitridesemiconductor substrate 10 a to have a thickness of a predeterminedvalue.

It is to be noted that the backside surface etching step may be carriedout after this step (S30) and before the topside surface grinding step(S40) described below. In this backside surface etching step, wetetching may be carried out, for example, using KOH as an etchingsolution. This is carried out in order to remove the damaged layer (forexample, having a thickness of 1-30 pin) formed on the backside surfaceof the substrate in the step (S30) described above. Accordingly, theetching amount is selected as appropriate in accordance with thethickness of the damaged layer. For example, the etching amount can beset at 1 μm or more and 30 μm or less.

Then, the topside surface grinding step (S40) is carried out.Specifically, in this step (S40), main surface 11 corresponding to thetopside surface of nitride semiconductor substrate 10 a is subjected tothe grinding process. This grinding process is carried out as apre-process of the polishing step described below. It is to be notedthat the conventionally well-known arbitrary method can be employed inthis topside surface grinding step (S40). Furthermore, the thickness ofthe damaged layer formed in this grinding step is, for example, 0.5 μmor more and 20 μm or less.

Then, the polishing step (S50) is carried out. In this step (S50), mainsurface 11 is ground by an arbitrary method. Consequently, main surface11 can be brought into a mirror-surface state. For example, in thepolishing step (S50), rough polishing and finish polishing may becarried out. This results in formation of a damaged layer on and aroundmain surface 11 (topside surface). The thickness of the damaged layermay be 0.1 μm or more and 5 μm or less, though varying depending on theconditions.

Then, the etching step (S60) is carried out. In this step (S60), atleast a part of the damaged layer in each of main surface 11 and thechamfered portion of nitride semiconductor substrate 10 a is removed byetching. An arbitrary method can be used as an etching method, and, forexample, dry etching may be used. For example, in this step (S60), whilethe damaged layer of main surface 11 is completely removed, the damagedlayer in the peripheral portion corresponding to the chamfered portionmay be remained to have a thickness of 1 μm or more and 3 μm or less. Itis to be noted that this etching step (S60) is not necessarily carriedout. It is preferable that the roughness of the main surface of thenitride semiconductor substrate is 10 nm or less in terms of Rastandards. It is preferable that the roughness of the backside surfaceis 10 μm or less in terms of Ra standards.

It is to be noted that the step of forming orientation flat 12 may becarried out before or after the step (S20). Specifically, although themethod for forming orientation flat 12 is not particularly limited, thenitride semiconductor substrate is subjected, for example, to cutting,grinding and the like in order to expose the (−1017) plane, the (10-1-7)plane, or the plane inclined at an angle of −0.5° or more and 0.5° orless from these planes.

Consequently, nitride semiconductor substrate 10 a shown in FIGS. 1 and2 can be obtained.

Referring to FIGS. 7-11, the modification of the nitride semiconductorsubstrate shown in FIGS. 1 and 2 will then be described.

Referring to FIG. 7, the modification of nitride semiconductor substrate10 a shown in FIGS. 1 and 2 is basically similar in structure to nitridesemiconductor substrate 10 a shown in FIGS. 1 and 2, but is different inshape of edge face 24. In other words, nitride semiconductor substrate10 a shown in FIG. 7 is provided with edge face 24 having a linear crosssection as shown in FIG. 7. The substrate having such a configurationalso allows the effects similar to those of nitride semiconductorsubstrate 10 a shown in FIGS. 1 and 2 to be obtained.

Referring to FIG. 8, another modification of nitride semiconductorsubstrate 10 a shown in FIGS. 1 and 2 is basically similar in structureto nitride semiconductor substrate 10 a shown in FIGS. 1 and 2, but isdifferent in shape of damaged layer 25 in the chamfered portion. Inother words, in nitride semiconductor substrate 10 a shown in FIG. 8,damaged layer 25 is formed only in topside chamfer 22. The substrate ofsuch a configuration also allows the effects similar to those of nitridesemiconductor substrate 10 a shown in FIGS. 1 and 2 to be obtained.

Nitride semiconductor substrate 10 a shown in FIG. 9 is basicallysimilar in structure to nitride semiconductor substrate 10 a shown inFIGS. 1 and 2, but is different in shape of the chamfered portion. Inother words, in nitride semiconductor substrate 10 a shown in FIG. 9,the width of backside chamfer 23 (the chamfering amount) is greater thanthe width of topside chamfer 22 (the chamfering amount) forming achamfered portion. The substrate of the above-described configurationalso allows the effects similar to those of nitride semiconductorsubstrate 10 a shown in FIGS. 1 and 2 to be obtained.

Nitride semiconductor substrate 10 a shown in FIG. 10 is anothermodification of nitride semiconductor substrate 10 a shown in FIGS. 1and 2, but is different in shape of the chamfered portion from nitridesemiconductor substrate 10 a shown in FIGS. 1 and 2. In other words, innitride semiconductor substrate 10 a shown in FIG. 10, the contour ofthe cross section of each of topside chamfer 22, backside chamfer 23 andedge face 24 constituting a chamfered portion has a curved shape. Thesubstrate of the above-described configuration also allows the effectssimilar to those of nitride semiconductor substrate 10 a shown in FIGS.1 and 2 to be obtained.

Nitride semiconductor substrate 10 a shown in FIG. 11 is basicallysimilar in configuration to nitride semiconductor substrate 10 a shownin FIGS. 1 and 2, but is different in shape of the chamfered portionfrom nitride semiconductor substrate 10 a shown in FIGS. 1 and 2. Inother words, in nitride semiconductor substrate 10 a shown in FIG. 11,topside chamfer 22 and backside chamfer 23 are almost equal in width.The substrate of the above-described configuration also allows theeffects similar to those of nitride semiconductor substrate 10 a shownin FIG. 1 to be obtained, for example, such as prevention of crackingand chipping occurring from the edge of the substrate. Furthermore, whentopside chamfer 22 and backside chamfer 23 are almost equal in width,the warpage of the nitride semiconductor substrate can be reduced.

Referring to FIGS. 12 and 13, another modification of the nitridesemiconductor substrate shown in FIGS. 1 and 2 will be described.

A nitride semiconductor substrate 10 b shown in FIG. 12 is basicallysimilar in configuration to nitride semiconductor substrate 10 a shownin FIGS. 1 and 2, but is different from nitride semiconductor substrate10 a in that nitride semiconductor substrate 10 b further includes asecond orientation flat 13.

Second orientation flat 13 serves as an IF (identification flat) or asub-orientation flat for providing an indication of an orientation andfor distinguishing between the topside surface and the backside surface.Second orientation flat 13 is approximately orthogonal to orientationflat 12. Second orientation flat 13 corresponds to the (11-20) plane(a-plane) or the plane inclined at an angle of −0.5° or more and 0.5° orless from this plane, and more preferably, corresponds to the (11-20)plane.

Referring to FIG. 13, the plane orientation of second orientation flat13 will be hereinafter described. As shown in FIG. 13, secondorientation flat 13 is at or near the (11-20) plane. The (11-20) planeis approximately orthogonal to the (20-21) plane or the (−202-1) plane,and also approximately orthogonal to the (−1017) plane or the (10-1-7)plane.

Second orientation flat 13 also allows the (11-20) plane or the planeinclined at an angle of −0.5° or more and 0.5° or less from this planeto be specified. It also allows the topside surface and the backsidesurface of nitride semiconductor substrate 10 b to be readilydistinguished from each other. Furthermore, cleavage readily occurs atand near the (11-20) plane where second orientation flat 13 cantherefore readily be provided. In the case where second orientation flat13 is at or near the (11-20) plane, the yield of the semiconductordevice can be further improved.

It is to be noted that the a-plane as described above includes and isequivalent to the (11-20) plane, the (1-210) plane, the (−2110) plane,the (−1-120) plane, the (−12-10) plane, the (2-1-10) plane, and theplane parallel to these planes. Furthermore, the [1-210] direction andthe [−12-10] direction in FIG. 3 extend in the a-axis direction. Thea-axis direction includes the [11-20] direction, the [1-210] direction,the [−2110] direction, the [−1-120] direction, the [−12-10] direction,the [2-1-10] direction, and the direction parallel to these directions.

It is preferable that a length L12 of orientation flat 12 is differentfrom a length L13 of second orientation flat 13. It is more preferablethat these lengths are different enough to allow the difference betweenthe lengths to be visually distinguished. Giving an example of the sizeof each of orientation flat 12 and second orientation flat 13, when thediameter of main surface 11 of nitride semiconductor substrate 10 b is,for example, 50 mm, orientation flat 12 has length L12 of, for example,2 mm or more and 30 mm or less, and second orientation flat 13 haslength L13 shorter than length L12 and of 2 mm or more and 20 mm orless, for example.

It is to be noted that the relative relationship between length L12 oforientation flat 12 and length L13 of second orientation flat 13 is nottaken into consideration.

As shown in FIG. 12, lengths L12 and L13 of orientation flat 12 andsecond orientation flat 13, respectively, correspond to each length ofthe linear areas in nitride semiconductor substrate 10 b as seen fromabove.

The method for manufacturing the nitride semiconductor substrate shownin FIG. 12 is basically similar in configuration to the method formanufacturing the nitride semiconductor substrate shown in FIGS. 1 and2, but is different in that it further includes the step of formingsecond orientation flat 13. Specifically, second orientation flat 13corresponding to the (11-20) plane or the plane inclined at an angle of−0.5° or more and 0.5° or less from this plane is formed before, afteror at the same time as formation of orientation flat 12.

As described above, nitride semiconductor substrate 10 b according tothe present embodiment further includes second orientation flat 13corresponding to the (11-20) plane or the plane inclined at an angle of−0.5° or more and 0.5° or less from this plane.

Cleavage tends to occur in the plane (11-20) or the plane inclined at anangle of −0.5° or more and 0.5° or less from this plane, where secondorientation flat 13 can therefore readily be formed. This also allowsthe topside surface and the backside surface of nitride semiconductorsubstrate 10 b to be distinguished from each other.

Referring to FIGS. 14 and 15, another modification of the nitridesemiconductor substrate shown in FIGS. 1 and 2 will be hereinafterdescribed. A nitride semiconductor substrate 10 c shown in FIGS. 14 and15 is basically similar in configuration to nitride semiconductorsubstrate 10 a shown in FIGS. 1 and 2, but is different in that itincludes a notch 15 as an indicator.

Notch 15 is a cutout portion provided at the outer periphery of nitridesemiconductor substrate 10 c. As shown in FIGS. 14 and 15, notch 15 isprovided in order to specify the (−1017) plane, the (−1017) plane, orthe plane inclined at an angle of −0.5° or more and 0.5° or less fromthese planes. Specifically, as shown in FIG. 15, when three points A, Band C are positioned in notch 15, the direction extending from theintermediate point between points B and C to point A corresponds to the[−1014] direction or the [10-1-4] direction.

As shown in FIG. 15, a depth H of notch 15 is, for example, 2 mm or moreand 10 mm or less, and an angle α is 30° or more and 120° or less. Inthe case where depth H is 10 mm or less and angle α is 120° or less, thearea of main surface 11 of nitride semiconductor substrate 10 c can beprevented from being reduced. In the case where depth H is 2 mm or moreand angle α is 30° or more, notch 15 can readily be identified.

The method for manufacturing nitride semiconductor substrate 10 c shownin FIGS. 14 and 15 is basically similar in configuration to the methodfor manufacturing nitride semiconductor substrate 10 a shown in FIGS. 1and 2, but is different in that notch 15 is provided in place oforientation flat 12. The method for providing notch 15 is notparticularly limited, but notch 15 can be provided by cutting, grinding,polishing, and the like.

Referring to FIG. 16, another modification of the nitride semiconductorsubstrate shown in FIGS. 1 and 2 will be hereinafter described.

A nitride semiconductor substrate 10 d shown in FIG. 16 is basicallysimilar in structure to nitride semiconductor substrate 10 c shown inFIGS. 14 and 15, but is different from nitride semiconductor substrate10 c shown in FIGS. 14 and 15 in that a second notch 16 is provided.

Second notch 16 is provided in order to provide an indication of anorientation and to distinguish between the topside surface and thebackside surface. The direction of second notch 16 is approximatelyorthogonal to the direction of notch 15. Second notch 16 serves toindicate the (11-20) plane or the plane inclined at an angle of −0.5° ormore and 0.5° or less from this plane, and more preferably, serves toindicate the (11-20) plane.

It is preferable that notch 15 and second notch 16 can be distinguishedfrom each other in that notch 15 corresponds to a main notch and secondnotch 16 corresponds to a sub-notch. For example, notch 15 may begreater than second notch 16 for the purpose of distinguishing them fromeach other.

The method for manufacturing nitride semiconductor substrate 10 d shownin FIG. 16 is basically similar in configuration to the method formanufacturing nitride semiconductor substrate 10 c shown in FIGS. 14 and15, but is different in that second notch 16 is further provided.

Referring to FIG. 17, another modification of the nitride semiconductorsubstrate shown in FIGS. 1 and 2 will be hereinafter described. Anitride semiconductor substrate 10 e shown in FIG. 17 is basicallysimilar in configuration to nitride semiconductor substrate 10 a shownin FIGS. 1 and 2, but is different in that a mark 17 is provided as anindicator.

Mark 17 is provided, for example, by application of a laser beam or byscratching by a diamond pen. Mark 17 is provided such that the (−1017)plane, the (10-1-7) plane, or the plane inclined at an angle of −0.5° ormore and 0.5° or less from these planes can be specified. For example, aplurality of marks 17 are provided in parallel with the [10-1-4]direction, the [−1014] direction or the direction inclined at an angleof −0.5° or more and 0.5° or less from these directions.

Furthermore, it is preferable that mark 17 is provided so as to allowthe (11-20) plane or the plane inclined at an angle of −0.5° or more and0.5° or less from this plane to be specified. For example, mark 17 inthe [−1014] or [10-1-4] direction is provided to vary in size, numberand the like from mark 17 in the [11-20] direction. In nitridesemiconductor substrate 10 e shown in FIG. 17, the number of marks 17 isgreater in the [11-20] direction than in the [−1014] direction.Consequently, the [−1014] direction and the [11-20] direction can beidentified.

Although marks 17 are provided in one place as a plurality of dots inFIG. 17, marks 17 may be provided in two or more regions, a single mark17 may be provided, and mark 17 may have a shape other than a dot.

It is preferable that mark 17 is provided in the plane on the sideopposite to the plane used for epitaxial growth in nitride semiconductorsubstrate 10 e. Even in the case where mark 17 is provided in thebackside surface and an impermeable metal film and the like are formed,since the nitride semiconductor has light transmissivity, its mainsurface is subjected to the polishing process to thereby allow mark 17provided in the backside surface to be readily recognized.

The method for manufacturing nitride semiconductor substrate 10 eaccording to the present embodiment is basically similar inconfiguration to nitride semiconductor substrate 10 a shown in FIGS. 1and 2, but is different in that mark 17 is provided in place oforientation flat 12.

Although the method for providing mark 17 is not particularly limited,for example, the method for providing a laser beam irradiation mark byapplying a laser beam or the method for providing a mark made byscratching by a diamond pen may be employed. Consequently, mark 17 canreadily be provided. Mark 17 can also be provided with an improvedprocessing accuracy.

Although orientation flat 12, notch 15 and mark 17 have been describedby way of an example of an indicator with regard to the above-describednitride semiconductor substrates 10 a-10 e, the indicator of the nitridesemiconductor substrate of the present invention is not particularlylimited thereto. Furthermore, the nitride semiconductor substrate of thepresent invention may include an orientation flat, a notch, a mark, andthe like in combination.

Second Embodiment

Referring to FIGS. 18 and 19, a light emitting element fabricated usingthe nitride semiconductor substrate according to the present inventionwill then be described.

Referring to FIG. 18, the light emitting element includes a nitridesemiconductor substrate 10 a corresponding to a GaN substrate of n-typeconductivity, an n-type GaN layer 41, an AlGaN layer 42 formed on n-typeGaN layer 41, a light emitting layer 43 formed on AlGaN layer 42, ap-type AlGaN layer 44 formed on light emitting layer 43, and a p-typeGaN layer 45 formed on p-type AlGaN layer 44. Nitride semiconductorsubstrate 10 a which is an n-type GaN substrate exhibitscharacteristics, for example, having a resistance value of 1×10⁻² Ωcmand a concentration of the n-type conductive impurities of 3×10¹⁸/cm³.For example, n-type GaN layer 41 can be configured to have a thicknessof 1 μm. Furthermore, silicon (Si) can be used as conductive impuritiescontained in this n-type GaN layer. For example, n-type AlGaN layer 42can be configured to have a thickness of 150 nm. For example, siliconcan be used as conductive impurities contained in this n-type AlGaNlayer 42. AlGaN layer 42 may have composition of Al_(0.1)Ga_(0.9)N, forexample.

Furthermore, a multiple quantum well structure, for example, as shown inFIG. 19 can be used as light emitting layer 43. Specifically, lightemitting layer 43 may have a multilayer structure obtained byalternately laminating GaN layer 43 a and GaInN layer 43 b. In thiscase, for example, GaN layer 43 a and GaInN layer 43 b may be configuredto have thicknesses of 10 nm and 3 nm, respectively. Furthermore, forexample, Ga_(0.85)In_(0.15)N can be used as composition of the GaInNlayer.

P-type AlGaN layer 44 located on this light emitting layer 43 can beconfigured to have a thickness of 20 nm. Furthermore, magnesium (Mg) canbe used as conductive impurities contained in this p-type AlGaN layer.For example, Al_(0.2)Ga_(0.8)N can be used as composition of this p-typeAlGaN layer 44.

Furthermore, p-type GaN layer 45 can be configured to have a thicknessof 150 nm. Also, magnesium can be used as conductive impuritiescontained in this p-type GaN layer 45.

The semiconductor element shown in FIGS. 18 and 19 can be formed bycarrying out the steps of preparing one of nitride semiconductorsubstrates 10 a-10 e according to the present invention by using themethod for manufacturing the substrate shown in FIG. 4, and then,epitaxially growing a predetermined film on main surface 11 of one ofnitride semiconductor substrates 10 a-10 e.

Then, as shown in FIG. 20, an electrode is formed on the topside surfaceand the backside surface of the semiconductor element shown in FIGS. 18and 19. Specifically, referring to FIG. 20, a p-side electrode 46 isformed on p-type GaN layer 45. For example, the electrode having alaminated structure of nickel (Ni) and gold (Au) can be used as thisp-side electrode 46. Furthermore, on the surface of nitridesemiconductor substrate 10 a made of n-type GaN, an electrode having alaminated structure made of titanium (Ti)/aluminum (Al)/titanium(Ti)/gold (Au) can be used as an n-side electrode 47, as shown in FIG.20. N-side electrode 47 is located approximately in the center of thesurface of nitride semiconductor substrate 10 a. P-side electrode 46 isformed so as to cover the surface of p-type GaN layer 45.

Then, the light emitting element fabricated in this way is attached to astem as shown in FIG. 21 to allow formation of a light emitting device.Referring to FIG. 21, p-side electrode 46 of the light emitting elementshown in FIG. 20 is fixedly connected to a stem 52 by solder 53. On theother hand, n-side electrode 47 is electrically connected to a lead pin51 through a wire 54. Thus, since the light emitting element mounted onstem 52 in the epi-down configuration (configuration in which theepitaxial layer side formed on nitride semiconductor substrate 10 a isconnected toward stem 52) has a transparent n-type GaN substratecorresponding to nitride semiconductor substrate 10 a (see FIG. 20),light can be emitted also from this substrate side to the outside.Furthermore, since light emitting layer 43 is positioned in the vicinityof stem 52, the heat generated from the light emitting layer is readilytransmitted to stem 52, which improves the heat dissipation performance.It is to be noted that the GaN substrate also has a high heatconductivity, which causes heat to be dissipated also from the substrateside.

The light emitting element can be configured to have a light emissionwavelength of 430 nm to 550 nm. The light emission wavelength can beadjusted by the In composition of the light emitting layer. According tothe nitride semiconductor substrate of the present invention, theefficiency of taking in of In during the epitaxial growth can beimproved, and thus, an excellent light emitting property can be achievedat a light emission wavelength of 500 nm to 550 nm in the green region.

A characteristic configuration of the present invention will behereinafter described, though partially overlapping the above-describedembodiments.

Nitride semiconductor substrates 10 a-10 e according to the presentinvention includes main surface 11 inclined at an angle of 71° or moreand 79° or less with respect to the (0001) plane toward the [1-100]direction or inclined at an angle of 71° or more and 79° or less withrespect to the (000-1) plane toward the [−1100] direction; and achamfered portion located at the edge of the outer periphery of mainsurface 11. The chamfered portion is inclined at an angle (θ1 or θ2) of5° or more and 45° or less with respect to one, which is adjacent to thechamfered portion, of main surface 11 and backside surface 21 on theside opposite to main surface 11.

Nitride semiconductor substrates 10 a-10 e according to the presentinvention each have main surface 11 which allows the yield to beimproved at the time when a semiconductor device is fabricated. Inaddition, cracking and chipping occurring from the edge of the outerperiphery of nitride semiconductor substrates 10 a-10 e can besuppressed. Consequently, defects occurring in nitride semiconductorsubstrates 10 a-10 e resulting from the above-mentioned cracking andchipping can be suppressed, and the yield of nitride semiconductorsubstrates 10 a-10 e can also be improved.

It is to be noted that main surface 11 is inclined at an angle of 71° ormore and 79° or less with respect to the (0001) plane toward the [1-100]direction or inclined at an angle of 71° or more and 79° or less withrespect to the (000-1) plane toward the [−1100] direction as describedabove since the yield of the semiconductor device can be improvedparticularly in this angle range. Furthermore, the lower limit ofinclination angle θ1 or θ2 of the chamfered portion is set at 5°. Thisis because, when the angle is smaller than this lower limit, theresultant angular portion at the edge of the outer periphery of thesubstrate is almost the same as that obtained in the case where nochamfered portion is substantially formed, with the result that noeffect of suppressing cracking and chipping can be achieved. Inaddition, the upper limit of the inclination angle is set at 45°. Thisis because, when the angle is greater than this upper limit, theresultant angular portion of the interface between the chamfered portionand the main surface shows an angle smaller than 135°, which produces aproblem of cracking and chipping in this angular portion.

It is to be noted that the inclination angle of the chamfered portion asdescribed above is preferably 15° or more and 35° or less, and morepreferably, 17° or more and 25° or less. The reason why the value rangeis set as described above is that it can increase the probability ofpreventing cracking, fracturing and chipping occurring in the subsequentsteps (the topside surface grinding and backside surface grindingsteps).

In the above-described nitride semiconductor substrates 10 a-10 e, mainsurface 11 may be inclined at an angle of −0.5° or more and 0.5° or lessfrom the (20-21) plane or the (−202-1) plane. In this case, each ofnitride semiconductor substrates 10 a-10 e having the above-mentionedplane as main surface 11 is used to fabricate a semiconductor device,which allows its characteristics to be particularly improved.

In the above-described nitride semiconductor substrates 10 a-10 e, adamaged layer 25 having an average thickness of 0.5 μm or more and 10 μmor less may be formed on the surface layer of the chamfered portion.

In this case, damaged layer 25 is formed at the edge of the outerperiphery of each of nitride semiconductor substrates 10 a-10 e tothereby allow the region having remaining stress to be provided at theedge of the outer periphery. Consequently, the effects of reducingdefects in shape such as warpage of nitride semiconductor substrates 10a-10 e can be achieved by adjusting the thickness of damaged layer 25 asappropriate.

It is to be noted that the average thickness of damaged layer 25 can bemeasured by a TEM (transmission electron microscope). The lower limit ofthe average thickness is set at 0.5 μm since, when forming a chamferedportion by polishing and grinding, the damaged layer having a thicknessless than 0.5 μm causes reduction in effects of suppressing warpage,which leads to a decrease in the yield of the device. Furthermore, theupper limit of the average thickness is set at 10 μm since the damagedlayer formed to have a thickness greater than 10 μm causes an increasein probability of occurrence of cracking and fracturing, which leads toa further decrease in the yield of the device.

It is to be noted that the average thickness of damaged layer 25 ispreferably 1 μm or more and 5 μm or less. The reason why the value rangeis set as described above is that the grindstone of a large grain sizeis used in the process where the average thickness is 1 μm or less,which increases the processing time to cause an increase inmanufacturing costs, and that the grindstone of a small grain size(coarser) is used in the process where the average thickness is 5 μm ormore, which causes a decrease in the yield of the device due to problemssuch as generation of particles.

In the above-described nitride semiconductor substrates 10 a-10 e, thechamfering amount of the chamfered portion (widths L1 and L2 in FIG. 2)may be 0.02 mm or more and 0.5 mm or less. In this case, the effects ofsuppressing cracking and chipping occurring from the edge of the outerperiphery of each of nitride semiconductor substrates 10 a-10 e can bereliably achieved.

In addition, the lower limit of the chamfering amount is set at 0.02 mm.This is because, when the value is smaller than this lower limit, theresultant angular portion at the edge of the outer periphery of thesubstrate is almost the same as that obtained in the case where nochamfered portion is substantially formed, with the result that noeffect of suppressing cracking and chipping can be achieved.Furthermore, the upper limit of the chamfering amount is set at 0.5 mm.This is because, when the chamfering amount is greater than this upperlimit, the area of the chamfered portion is excessively increased in themain surface of the substrate to thereby cause a decrease in the numberof semiconductor devices obtained from the substrate, which results inan increase in manufacturing costs of the semiconductor device.

It is to be noted that the above-described chamfering amount ispreferably 0.05 mm or more and 0.3 mm or less, and more preferably, 0.05mm or more and 0.2 mm or less. The reason why the value range is set asdescribed above is that a greater chamfering amount (leading to anincrease in the grinding amount) causes an increased load to be appliedto the substrate during processing, which leads to an increase in theprobability of occurrence of defects such as cracking and the like.

In the above-described nitride semiconductor substrates 10 a-10 e, thearithmetical mean roughness (Ra) in the topside surface of the chamferedportion may be 0.07 μm or more and 3 μm or less.

In this case, it can be possible to prevent problems from occurring (forexample, generation of particles) due to excessive roughness of thesurface of the chamfered portion. It is to be noted that the lower limitof the above-mentioned surface roughness is set at 0.07 μm in terms ofRa since it is difficult to reduce the surface roughness below thislower limit at reasonable costs. Furthermore, the upper limit of theabove-mentioned surface roughness is set at 3 μm in terms of Ra sincethe value greater than this upper limit causes an increased probabilityof occurrence of problems such as generation of particles.

Furthermore, the above-mentioned surface roughness is, in terms of Ra,preferably 0.07 μm or more and 1 μm or less, and more preferably, 0.07μm or more and 0.5 μm or less. The reason why the value range is set asdescribed above is that the smaller the Ra is, the finer the particles(impurities) can be suppressed from occurring, which leads to anincrease in the yield of the device element.

In the above-described nitride semiconductor substrates 10 a-10 e, mainsurface 11 may be subjected to mirror-surface processing. The surfaceroughness of main surface 11 may be 0.2 nm or more and 4 nm or less interms of the root mean square roughness (RMS).

In this case, when an epitaxial film is formed on main surface 11,formation defects in the epitaxial film can be suppressed.

It is to be noted that the lower limit of the surface roughness of mainsurface 11 is set at the above-described values since it is difficult toset the surface roughness below the above-described values atindustrially reasonable costs. Furthermore, the upper limit of theabove-described surface roughness is set at the above-described valuessince the value greater than the above-described values causes anincreased probability of occurrence of formation defects in theepitaxial film.

Furthermore, the above-described surface roughness of main surface 11 ispreferably 1 nm or more and 3 nm or less in terms of RMS. The reason whythe value range is set as described above is that this value range ispreferable in terms of costs and quality as with the reasons describedabove.

An indicator (orientation flats 12 and 13, notches 15 and 16, mark 17)indicating a predetermined plane may be provided in the above-describednitride semiconductor substrates 10 a-10 e.

In this case, when nitride semiconductor substrates 10 a-10 e aretreated or when nitride semiconductor substrates 10 a-10 e are used tomanufacture a semiconductor device (see FIGS. 18-21), the planeorientation of each of nitride semiconductor substrates 10 a-10 e can bereliably recognized.

In the above-described nitride semiconductor substrates 10 a-10 e, thepredetermined plane indicated by the indicator may be the (−1017) plane,the (10-1-7) plane, or the plane inclined at an angle of −0.5° or moreand 0.5° or less from these planes, or may be the (11-20) plane or theplane inclined at an angle of −0.5° or more and 0.5° or less from thisplane.

Nitride semiconductor substrates 10 a-10 e according to the presentinvention each have main surface 11 that allows the yield to be improvedwhen a semiconductor device is fabricated. As a result of an earneststudy to specify the plane orientation for the purpose of applyingnitride semiconductor substrates 10 a-10 e each having main surface 11to a semiconductor device, the inventors of the present invention foundthat the (−1017) plane and the (10-1-7) plane and their vicinities tendto readily cleave. Then, the inventors first revealed that the (−1017)plane, the (10-1-7) plane, or the plane inclined at an angle of −0.5° ormore and 0.5° or less from these planes is identified by the indicator.This indicator allows the plane to be specified, which is readilycleaved when fabricating a semiconductor device using nitridesemiconductor substrates 10 a-10 e each having this main surface 11.Accordingly, the crystal orientation can be aligned or distinguished byusing the plane that is readily cleaved. Thus, a semiconductor deviceexhibiting improved characteristics can be fabricated by using nitridesemiconductor substrates 10 a-10 e according to the present invention.Therefore, nitride semiconductor substrates 10 a-10 e according to thepresent invention can be used for a semiconductor device.

The method for manufacturing a nitride semiconductor substrate accordingto the present invention includes the step (S 10) of preparing a nitridesemiconductor substrate having a main surface inclined at an angle of71° or more and 79° or less with respect to the (0001) plane toward the[1-100] direction or inclined at an angle of 71° or more and 79° or lesswith respect to the (000-1) plane toward the [−1100] direction; and thestep (S20) of chamfering the edge of the outer periphery of the mainsurface of the nitride semiconductor substrate. The step (S20) ofchamfering the edge includes the step of forming a chamfered portioninclined at an angle (θ1 or θ2) of 5° or more and 45° or less withrespect to one, which is adjacent to the chamfered portion, of mainsurface 11 and backside surface 21 on the side opposite to main surface11. In this way, nitride semiconductor substrates 10 a-10 e according tothe present invention can be manufactured.

The semiconductor device according to the present invention isfabricated using each of the above-described nitride semiconductorsubstrates 10 a-10 e, as shown in FIGS. 18-21. In this case, sincecracking and chipping occurring in nitride semiconductor substrates 10a-10 e can be effectively suppressed, a semiconductor device exhibitinga high manufacturing yield can be implemented.

The method for manufacturing a semiconductor device according to thepresent invention includes the steps of preparing nitride semiconductorsubstrates 10 a-10 e using the method for manufacturing theabove-described nitride semiconductor substrate as shown in FIG. 4; andforming an epitaxial layer on main surface 11 of each of nitridesemiconductor substrates 10 a-10 e. In this case, since cracking andchipping occurring in nitride semiconductor substrates 10 a-10 e areeffectively suppressed, a semiconductor device exhibiting a highmanufacturing yield can be implemented.

Example 1

In this example, the usability of the GaN substrate cut out from the(0001) GaN ingot in the [1-100] direction at an angle θ in the rangebetween 68° and 82° was examined (Test 1). Specifically, the substratewith an angle different from angle 8 was used to form an element of asemiconductor laser device and measure the oscillation yield of theelement. Furthermore, an examination was made with regard to the effectsof the inclination angle (θ1 or θ2) of the chamfered portion withrespect to adjacent one of main surface 11 and backside surface 21 onthe side opposite to main surface 11 (Test 2).

(Test 1)

Preparation of Sample

First, the (0001) GaN ingot thickly grown by the HYPE method was cut atan angle θ in the range between 68° and 82° in the [1-100] directionusing a wafer slicing apparatus to fabricate a GaN substrate (sample IDsin Table 1 set forth below: I-1 to I-9) in which an inclination angle θformed between the [0001] direction and the [1-100] direction has adesired off angle in the range between 68° and 82°. For example, whenthe ingot was cut at angle θ of 75°, a GaN substrate having the (20-21)plane as a main surface was obtained. This main surface corresponds tomain surface 11 in the hexagonal crystal lattice in FIG. 3.

In the GaN substrate, a chamfered portion was formed at its edge of theouter periphery. In addition, when a resin bond grindstone is used forchamfering processing, fracturing or cracking may occur from the outerperiphery of the GaN substrate. Thus, in the present example, a rubbergrindstone was used for processing in order to prevent fracturing andcracking. Specifically, the outer periphery was ground using agrindstone in which a mixture of 40 wt % of diamond abrasive grainshaving a grain size of #1000 and 60 wt % of Fe₂O₃ abrasive grains wasfixed to the base with CR (chloroprene rubber). In this case, thearithmetical mean roughness (Ra) of the topside surface was 0.1 μm. Therubber grindstone has a porosity of 0% and has a thickness equal to thatof the substrate. The shape of the chamfered portion (chamfer shape) wasformed based on the shape shown in FIG. 11 in which the shapes on thetopside and the backside were symmetrical to each other. The angle ofthe chamfer (chamfered angle) was uniformly set at 20°, and thechamfering amount was uniformly set at 0.2 mm. It is to be noted thatwhen the substrate thickness, the chamfered angle of the topside andbackside surfaces, and the chamfering amount are determined, theremaining length is also determined, and accordingly, the chamfers canbe connected to each other by a smooth curved surface.

Furthermore, an orientation flat corresponding to the (−1017) plane wasformed in this GaN substrate.

Then, the GaN substrate was used to form a semiconductor laser device bythe metal organic chemical vapor deposition method. A resultantsemiconductor laser device 100 has a configuration shown in FIGS. 22 and23. Furthermore, the materials used in the metal organic chemical vapordeposition method include trimethyl gallium (TMGa), trimethyl aluminum(TMAl), trimethyl indium (TMIn), ammonia (NH₃), and silane (SiH₄).

Specifically, after the GaN substrate was placed as nitridesemiconductor substrate 10 a on the susceptor in the reactor, anepitaxial layer was grown in the following growth process. First,referring to FIG. 22, n-type GaN having a thickness of 1000 nm was grownas an n-type buffer layer 102 on the main surface of nitridesemiconductor substrate 10 a (GaN substrate). Then, an n-type InAlGaNcladding layer having a thickness of 1200 nm was grown as an n-typecladding layer 103. Then, an n-type GaN guide layer having a thicknessof 200 nm as an n-type guide layer 104 and an undoped InGaN guide layerhaving a thickness of 65 nm as an undoped guide layer 105 were grown.Then, a 3-cycle MQW structure made of GaN having a thickness of 15 nmand InGaN having a thickness of 3 nm was grown as an active layer 106.Then, an undoped InGaN guide layer having a thickness of 65 nm as anundoped guide layer 107, a p-type AlGaN block layer having a thicknessof 20 nm as a p-type block layer 108, and a p-type GaN guide layerhaving a thickness of 200 nm as a p-type guide layer 109 were grown.Then, a p-type InAlGaN cladding layer having a thickness of 400 nm wasgrown as a p-type cladding layer 110. Finally, a p-type GaN contactlayer having a thickness of 50 nm was grown as a p-type contact layer111.

Then, after forming an insulation film 112 made of SiO₂ on p-typecontact layer 111, the photolithography method was used to provide astripe window having a width of 10 μm in insulation film 112 by wetetching. In this case, since the [−1014] direction can be specified inthe above-described epitaxial layer by orientation flat 12, thedirection of the laser stripe was inclined at an angle of −0.5° or moreand 0.5° or less from the [−1014] direction, as shown in FIG. 23.

Since an opening (stripe window) of insulation film 112 is provided inthe above-described direction, the orientation of a waveguide 100 c ofsemiconductor laser device 100 is in the [−1014] direction or isinclined at an angle of −4° or more and 4° or less with respect to thisdirection toward the [1-100] direction, and is inclined at an angle of−0.5° or more and 0.5° or less in the direction orthogonal to the[1-100] direction, as shown in FIG. 23. In other words, waveguide 100 cis formed in the direction approximately vertical to end faces 100 a and100 b (the (−1017) plane, the (10-1-7) plane, or the plane inclined atan angle of −4° or more and 4° or less with respect to these planestoward the [1-100] direction and inclined at an angle of −0.5° or moreand 0.5° or less in the direction orthogonal to the [1-100] direction).

Then, after providing the stripe window, a p-type electrode 113 made ofNi/Au and a pad electrode (not shown) made of Ti/Al werevapor-deposited. Then, by using the diamond slurry, the backside surfaceof the GaN substrate (nitride semiconductor substrate 10 a) was groundto achieve a substrate thickness of 100 μm or less which facilitatescleavage, and fabricate a substrate product having a backside surface inthe mirror state. On the backside surface (polishing surface) of the GaNsubstrate, an n-type electrode 114 made of Ti/Al/Ti/Au was formed byvapor deposition.

A resonator mirror for this laser stripe was fabricated using a laserscriber employing a YAG laser beam having a wavelength of 355 nm. Whenthe laser scriber is used for cutting, the oscillation chip yield can beimproved as compared to the case where the diamond scribe method isused. A scribe groove was formed on the conditions that the laser lightoutput was set at 100 mW and the scanning speed was set at 5 mm/s. Forexample, the resultant scribe groove had a length of 30 μm, a width of10 μm and a depth of 40 μm. The scribe groove was formed by directlyapplying a laser light beam to the surface of the epitaxial layer at apitch of 800 μm through an opening in the insulation film of the GaNsubstrate. The resonator length was set at 600 μm.

A resonator mirror was fabricated by cutting using a blade. The bladewas pressed against the underside of the GaN substrate to cut thesubstrate product, thereby fabricating a laser bar. More specifically,as shown in FIG. 24, end faces 100 a and 100 b for a laser resonatorcorrespond to the (−1017) plane and the (10-1-7) plane, respectively.Main surface 11, end faces 100 a and 100 b are different from theconventional cleavage plane such as the conventional c-plane, m-planeand a-plane, respectively.

As a result of observation, with a scanning electron microscope, of theplane provided by cutting, noticeable projections and depressions werenot observed. Accordingly, it is presumed that the degree of flatness ofthe plane obtained by cutting (size of projections and depressions) is20 nm or less. Furthermore, the vertical degree with respect to thesample surface of the above-described plane fell within a range of ±5°.

Then, the end face of the laser bar was coated with a dielectricmultilayer film by the vacuum deposition method. The dielectricmultilayer film was formed by alternately laminating SiO₂ (siliconoxide) and TiO₂ (titanium dioxide). The film thickness was adjusted tofall within a range of 50 nm or more and 100 nm or less, to design thecenter wavelength of the reflectivity to fall within a range of 500 nmor more and 530 nm or less. On one side, the reflecting plane was set to10 cycles and the design value of the reflectivity was set at about 95%.On the other side, the reflecting plane was set to 6 cycles and thedesign value of the reflectivity was set at about 80%.

Test and Results

With regard to the semiconductor laser device fabricated as describedabove, the relationship between inclination angle θ of the main surfaceof the GaN substrate (angle of the main surface) with respect to the(0001) plane toward the [1-100] direction and the oscillation yield wasexamined. In the present example, the oscillation yield was defined as(the number of oscillation chips)/(the number of measurement chips). Theresults are shown in Table 1.

TABLE 1 ID I-1 I-2 I-3 I-4 I-5 I-6 I-7 I-8 I-9 Angle of Main Surface (°)82 79 77 76 75 74 73 71 68 Angle of Chamfer (°) 20 20 20 20 20 20 20 2020 Element Yield (%) 15 51 77 84 85 82 75 50 10

Table 1 shows that excellent results were obtained in that theoscillation yield was 50% or more when inclination angle θ of the GaNsubstrate formed between the direction and the [1-100] direction (theangle of the main surface described in Table 1) fell within a range of71° or more and 79° or less.

(Test 2)

In Test 2, an experiment was made basically with regard to the substratehaving the above-described inclination angle θ (the angle of the mainsurface) of 75°. Specifically, the element yield and the substrate yieldwere examined with the topside and backside surfaces at differentangles. The substrate yield, which corresponds to the percentage bywhich the substrate suffers no cracking, fracturing and chipping, wasdefined as (the number of substrates suffering no cracking, fracturingand chipping observed by visual confirmation)/(the number of themeasured substrates).

Preparation of Sample

Samples of the GaN substrate (sample IDs in Table 2 described below:II-1 to II-11) and samples of the semiconductor laser device werefabricated by the method basically similar to that used for fabricatingthe samples prepared in Test 1 as described above. However, as shown inTable 2 describe below, the angle of the main surface (inclination angleθ) was set at 75°, 71° or 79°. Furthermore, with regard to each sample,the chamfered angle of the chamfered portion was changed in the range of0° to 60°, as shown in Table 2. In this case, the grindstone having agrain size of #1000 was used for chamfering. Furthermore, the substratehaving the same thickness was used. The shape of the chamfered portion(chamfer shape) was formed based on the shape shown in FIG. 11 in whichthe shapes on the topside and the backside were symmetrical to eachother. The chamfering amount was uniformly set at 0.2 mm.

Test and Results

With regard to the samples of the GaN substrate fabricated as describedabove, the substrate yield was calculated by visually observing thesituation in which defects such as cracking, fracturing and chippingoccur. Furthermore, with regard to the semiconductor laser devicefabricated using each sample of the GaN substrate, the oscillation yield(element yield) was measured in the same manner as in Test 1. Theresults are shown in Table 2.

TABLE 2 ID II-1 II-2 II-3 II-4 II-5 II-6 II-7 II-8 II-9 II-10 II-11Angle of Main 75 75 75 75 75 75 75 71 71 79 79 Surface (°) Angle of 0 515 25 35 45 60 5 45 5 45 Chamfer (°) Element 85 84 83 84 85 84 83 51 5052 51 Yield (%) Substrate 11 65 72 90 69 60 25 59 60 62 61 Yield (%)

As shown in Table 2, the excellent results were obtained in that thesubstrate yields was 50% or more when the chamfered angle was 5° or moreand 45° or less. Furthermore, the similar results were obtained alsowhen using the chamfered portion having the chamfering amount and thechamfered angle each different between the topside surface and thebackside surface.

Furthermore, the similar results were obtained also when the angle ofthe main surface (inclination angle θ) fell within the range of 71° and79°. Also with regard to the crystal grown by the flux method, the sameresults as those described above were obtained. Furthermore, the sameresults as those described above were obtained also when a plurality ofGaN substrates were used for an underlying substrate to grow a singleGaN crystal on the plurality of underlying substrates by the HYPEmethod.

Example 2

In the present example, under different processing conditions for thechamfered portion (chamfering processing conditions), the substratehaving a damaged layer of a different thickness in the chamfered portionwas used to examine the effects caused by the thickness of the damagedlayer. Specifically, samples of the GaN substrate having a damaged layerof a different thickness in the chamfered portion were prepared. Then, asemiconductor laser device having the same structure as in Example 1 wasfabricated using the GaN substrate, and the element yield was examined.

Preparation of Sample

Samples of the GaN substrate (sample IDs in Table 3 described below:III-1 to III-9) were fabricated basically by the same manufacturingmethod as that of the GaN substrate in Example 1. The thickness of thedamaged layer was changed by adjusting the grain size and the like ofthe rubber grindstone used for chamfering processing. Furthermore, theGaN substrate was configured to have a main surface inclined at angle θ(angle of the main surface) of 75° or 73° with respect to the (0001)plane toward the [1-100] direction.

Then, the resultant GaN substrate was used to fabricate a semiconductorlaser device as in Example 1. Furthermore, the substrate having the samethickness was used, and the shape of the chamfered portion (chamfershape) was formed based on the shape shown in FIG. 11 in which theshapes on the topside and the backside were symmetrical to each other.The chamfered angle was uniformly set at 20° and the chamfering amountwas uniformly set at 0.2 mm.

Test and Results

With regard to the manufactured semiconductor laser device, anoscillation experiment was conducted to examine the relationship betweenthe thickness of the damaged layer in the chamfered portion (the averagedamaged layer thickness) and the oscillation yield (element yield). Theresults are shown in Table 3.

TABLE 3 ID III-1 III-2 III-3 III-4 III-5 III-6 III-7 III-8 III-9 Angleof Main Surface (°) 75 75 75 75 75 75 75 73 73 Thickness of Damagedlayer 0.5 1 3 5 7 9 11 1 11 in Chamfer(μm) Element Yield (%) 50 85 86 8453 51 13 73 11

As shown in Table 3, the excellent results were obtained in that theelement yields was 50% or more when the average damaged layer thicknessin the chamfer was 0.5 μm or more and 10 μm or less. Furthermore, thesame results were obtained also when using the chamfered portion havingthe chamfering amount and the chamfered angle each different between thetopside surface and the backside surface. Also with regard to thecrystal grown by the flux method, the same results as those describedabove were obtained. Furthermore, the same results as those describedabove were obtained also when a plurality of GaN substrates were usedfor an underlying substrate to grow a single GaN crystal on theplurality of underlying substrates by the HVPE method.

Example 3

In the present example, under different processing conditions for thechamfered portion (chamfering processing condition), the substratehaving a chamfered portion chamfered by a different amount was used toexamine the effects caused by the chamfering amount. Specifically,samples of the GaN substrate having a chamfered portion chamfered by adifferent amount were prepared to examine the substrate yield.

Preparation of Sample

Samples of the GaN substrate (sample IDs in Table 4 described below:IV-1 to IV-9) were fabricated basically by the same manufacturing methodas that of the GaN substrate in Example 1. Inclination angle θ of themain surface of the GaN substrate (angle of the main surface) withrespect to the (0001) plane toward the [1-100] direction was set at 75°or 74°. In this case, the grindstone having a grain size of #1000 wasused for chamfering. Furthermore, the substrate having the samethickness was used, and the shape of the chamfered portion (chamfershape) was formed based on the shape shown in FIG. 11 in which theshapes on the topside and the backside were symmetrical to each other.The chamfered angle was uniformly set at 20°.

Test and Results

With regard to the samples of the GaN substrate fabricated as describedabove, the substrate yield was calculated by visually observing thesituation in which defects such as cracking, fracturing and chippingoccur. The results are shown in Table 4.

TABLE 4 ID IV-1 IV-2 IV-3 IV-4 IV-5 IV-6 IV-7 IV-8 IV-9 Angle of MainSurface (°) 75 75 75 75 75 75 75 74 74 Chamfering Amount (mm) 0 0.020.05 0.1 0.2 0.5 0.6 0.1 0.6 Substrate Yield (%) 8 65 80 90 89 53 25 8820

As shown in Table 4, the excellent results were obtained in that thesubstrate yields was 50% or more when the chamfering amount was 0.02 mmor more and 0.5 mm or less. Furthermore, the same results were obtainedalso when using the chamfered portion having the chamfering amount andthe chamfered angle each different between the topside surface and thebackside surface. Also with regard to the crystal grown by the fluxmethod, the same results as those described above were obtained.Furthermore, the same results as those described above were obtainedalso when a plurality of GaN substrates were used for an underlyingsubstrate to grow a single GaN crystal on the plurality of underlyingsubstrates by the HVPE method.

Example 4

In the present example, under different processing conditions for thechamfered portion (chamfering processing condition), the substratehaving a chamfered portion of a different surface roughness was used toexamine the effects caused by the surface roughness. Specifically,samples of the GaN substrate having a chamfered portion of a differentsurface roughness were prepared. The GaN substrate was then used tofabricate a semiconductor laser device having the same structure as thatin Example 1, to examine the element yield.

Preparation of Sample

Samples of the GaN substrate (sample IDs in Table 5 described below: V-1to V-9) were fabricated basically by the same manufacturing method asthat of the GaN substrate in Example 1. In addition, the arithmetic meanroughness (Ra) of the surface of the chamfered portion was changed byadjusting the grain size and the like of the rubber grindstone used forchamfering processing. Furthermore, the GaN substrate was configured tohave a main surface inclined at angle θ (angle of the main surface) of75° or 76° with respect to the (0001) plane toward the [1-100]direction. The substrate having the same thickness was used. The shapeof the chamfered portion (chamfer shape) was formed based on the shapeshown in FIG. 11 in which the shapes on the topside and the backsidewere symmetrical to each other. The chamfered angle was uniformly set at20° and the chamfering amount was uniformly set at 0.2 mm.

Then, the resultant GaN substrate was used to fabricate a semiconductorlaser device in the same manner as in Example 1.

Test and Results

With regard to the manufactured semiconductor laser device, anoscillation experiment was conducted to examine the relationship betweenthe surface roughness of the chamfered portion (roughness of thechamfer) and the oscillation yield (element yield). The results areshown in Table 5.

TABLE 5 ID V-1 V-2 V-3 V-4 V-5 V-6 V-7 V-8 V-9 Angle of Main Surface (°)75 75 75 75 75 75 75 76 76 Roughness of Chamfer 0.07 0.1 0.5 1 2 3 4 0.13 Ra (μm) Element Yield (%) 91 88 86 62 55 52 12 90 51

As shown in Table 5, the excellent results were obtained in that theelement yields was 50% or more when the surface roughness of thechamfered portion was 0.07 or more and 3 μm or less. Furthermore, thesame results were obtained also when using the chamfered portion havingthe chamfering amount and the chamfered angle each different between thetopside surface and the backside surface. Also with regard to thecrystal grown by the flux method, the same results as those describedabove were obtained. Furthermore, the same results as those describedabove were obtained also when a plurality of GaN substrates were usedfor an underlying substrate to grow a single GaN crystal on theplurality of underlying substrates by the HVPE method.

The present invention is particularly advantageously applied to anitride semiconductor substrate having a main surface serving as asemipolar plane and a semiconductor device fabricated using this nitridesemiconductor substrate.

Although the present invention has been described and illustrated indetail, it is clearly understood that the same is by way of illustrationand example only and is not to be taken by way of limitation, the scopeof the present invention being interpreted by the terms of the appendedclaims.

1-5. (canceled) 6: A method for manufacturing a nitride semiconductorsubstrate, comprising the steps of: preparing a nitride semiconductorsubstrate having a main surface inclined at an angle of 71° or more and79° or less with respect to a (0001) plane toward a [1-100] direction orinclined at an angle of 71° or more and 79° or less with respect to a(000-1) plane toward a [−1100] direction; and chamfering an edge of anouter periphery of said main surface of said nitride semiconductorsubstrate, said step of chamfering the edge includes the step of forminga chamfered portion inclined at an angle of 5° or more and 45° or lesswith respect to adjacent one of said main surface and a backside surfaceon a side opposite to said main surface. 7: A method for manufacturing asemiconductor device, comprising the steps of: preparing a nitridesemiconductor substrate using the method for manufacturing a nitridesemiconductor substrate according to claim 6; and forming an epitaxiallayer on said main surface of said nitride semiconductor substrate.